TC7100: 3GPP turbo decoder
TC7100 is a convolutional turbo code (CTC) decoder optimized for 3GPP specifications. All turbo code options specified in 3GPP are covered with full block size coverage. The Core is self-contained and does not require external memory banks. The decoded throughput is typically 15 Mbits/s. The Core is available for FPGA or ASIC implementation, and is silicon-proven.
Features
- Compliant with 3GPP specifications
- Block size : 40 to 5144 bits, switchable on the fly
- Near floating point error correction performance
- Selection between Max-Log-MAP and Log-MAP algoritms
- Optimal iteration stopping feature for reducing average number of iterations
- On-the-fly change of block length and number of iterations
- Low latency
- Single FPGA Core (no external memory required), available on all popular Xilinx, Altera and Lattice devices
- ASIC Core : Verilog or VHDL RTL Core delivery
- Silicon-proven
