TC4000: DVB-S2 decoder

Our TC4000 LDPC+BCH decoder implements a powerful FEC scheme leading to "Close-to-Shannon" Eb/N0 performance. It is fully compliant with DVB-S2 specifications (ETSI EN 302307) and is based on TurboConcept's advanced LDPC decoder architecture. The Core performs the following functions:

I/Q demapping into soft-LLR values - supports QPSK, 8PSK, 16 and 32 APSK
Block deinterleaver (8PSK and APSK modulations)
Fast-Iterative LDPC decoding
BCH decoding
Optional base-band functions - descrambling, CRC decoding, TS interface

The FEC encoder is also available, either as a stand-alone Core or integrated into Commsonic DVB-S2 modulator solution

Decoder Core features:

Supports CCM, VCM, ACM modes
30, 45, and 63 Mbaud versions available (other profiles available)
Supports 16kbit and 64kbit frames
Efficient device logic utilization
Optional bit-LLR input for use with other modulations
Syndrome-based LDPC iteration stopping
Frame-by-frame programmability of code rate, modulation, block size
Frame error detection indication
Built-in SNR estimation
Frame counter for NCR synchronization
Interface with Commsonic CMS0014 DVB-S2 demodulator Core
Available on FPGA, Structured ASIC or ASIC.