TC6000: CCSDS Turbo decoder
FEC TECHNOLOGY: CCSDS
- Parallel concatenation, convolutional codes, 16 states
- Trellis based on binary input
FEATURES:
- Flexible block size: all CCSDS defined from 1784 to 8920 bits (extensible to 16384 bits). Switchable on-the-fly
- Flexible coding ratio: all CCSDS defined 1/2,1/3,1/4,1/6. Switchable on-the-fly
- Number of iterations: 2 to 16. Switchable on-the-fly
- Optional Cyclic Redundancy Check (CRC). Switchable-on-the-fly
- Log-MAP decoding algorithm for best coding gain
- Single-chip FPGA Core, no external memory required
- Latency reduction by bank-swapping (2 input buffers)
- In-operation channel BER monitoring
- Micro-controller interface.