TC7000-LTE: 3GPP-Long Term Evolution (LTE) turbo decoder

TC7000-LTE is a convolutional turbo code (CTC) decoder optimized for 3GPP/LTE specifications. It offers several algorithm options to meet various trade-offs between error correction performance versus Core complexity. The decoder architecture is high-throughput oriented for all block sizes. Four throughput profiles are available, through parallel decoding architecture(*):

1-processor Core : 25 Mbps
2-processors Core : 50 Mbps
4-processors Core : 100 Mbps
8-processors Core : 200 Mbps

(*) Throughput depends on the selected device and vary with the block size and number of iterations. Typical figures given with 4 decoding iterations. Please contact TurboConcept for additional information.

FEATURES:

Deliverables include encoder and decoder Cores.
Compliant with 3GPP-LTE

Block size covered from 40 to 6144 payload bits, switchable on the fly
Sub-block deinterleaver included.
CRC check included.

Near floating point error correction performance
High throughput Max-Log-MAP algorithm
Efficient and flexible optional Log-MAP algorithm
Multi-processor architecture, several throughput levels selectable before synthesis - from 25 to over 200 Mbps decoded
Optimal iteration stopping feature for reducing average number of iterations without performance degradation
On-the-fly change of block length and number of iterations
Low latency
Single FPGA Core (no external memory required), available on all popular Xilinx, Altera and Lattice devices
ASIC Core : Verilog or VHDL RTL Core delivery
Silicon proven